Description: |
Our client seeks an experienced Physical /Layout design engineer for Full Custom CMOS layout of complex RF/Analogue mixed mode ASICs for wireless communications. You will aid and assist the Head of Physical Design in the layout, top level assembly and tape out of RF/Analogue mixed mode ASIC's in a number of Deep Sub Micron CMOS technologies. Main tasks will include:- 'Tape out' completed database and all the associated documentation and checks. Floor planning of complete chips/complex blocks. Generation of Outline Cell for digital Place and Route tools and Padring. Layout of complex/critical blocks and cells. Full verification of all of the above. Understand and set up new fabrication processes/design rules as they are adopted. Provide quick and accurate chip size estimates based on 'what if' criteria. Guide, advise and train members of the design team in best layout practice. Ideally you will have five plus year's experience (more preferably) of CMOS Deep Sub Micron (0.18um and 0.13um) Full Custom IC layout and verification. This will range from the layout of standard library cells, through RF/Analogue block level, to top level pad ring and final chip assembly, verification and tape out. Experience in the following tools is sought:- Full Custom Tools: Tanner - L-Edit, Avanti - Enterprise, Mentor Graphics - IC Station, Cadence Verification Tools: Calibre, Dracula, Diva, xCalibre, Star RC-XT You must also be able to demonstrate expertise of the use and interpretation of DRC, LVS and back annotated extraction results. In addition the candidate will have previous experience in configuring and developing CAD tools and process set up, have the ability to work independently, or part of a team or be able to lead a small group. Experience with C, C++, or Skill would be advantageous. Additional programming language skills (C, C++, Skill) to be considered an advantage. A competitive salary is on offer including share options, non-contributory pension, medical insurance & health insurance. |
